The year is 2026. You, a passionate hardware engineer, sit down at your desk and open up your laptop to start work. First, you open up a remote VNC session displaying a laggy Linux desktop from 2005. Then, you open up a proprietary set of domain-specific software tools to begin your work, whether it is writing RTL (e.g. running sims), performing design verification (e.g. debugging waves), or creating the physical design (e.g. placing and routing).
For most semiconductor companies working at scale, such bespoke proprietary flows are entrenched. There are some notable exceptions — especially for companies which have sprung up relatively recently and/or are working at a lower scale — but they are far from being the default today. Thus, for software engineers used to modern OSS tooling, even something as basic as the version control system (Git is not as ubiquitous as you might think!) would be taken for granted as an "assumed tool".
So, why is this the case? And how did we get here?
A Brief History of EDA
Before diving into the history, I want to first emphasize that SW flows for HW are rapidly evolving, as more and more HW development relies on scalable SW infrastructure (e.g. large-scale build systems, CI/CD, storage systems, cloud-based compute farms, etc.). That being said, this change needs to be taken in the context of the semiconductor industry's long history, which differs quite significantly from that of pure SW companies.
Historically, the semiconductor industry has relied on EDA (electronic design automation) and CAD (computer-aided design) tools to help with each portion of the chip development lifecycle. These tools encompass everything from GUI-based visualizations of layouts to CLI tools and libraries for logic synthesis. I find it helpful to think of this process as not unlike a scientist who interacts with domain-specific software as part of their job (even if their core expertise is not necessarily in SW itself).
There is a growing movement within the HW industry to promote OSS trends, and it is exciting to watch:
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RISC-V
An open ISA avoiding ARM/x86 license costs, gaining significant industry traction
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OSS alternatives to common proprietary tools
A growing collection of open-source replacements across the EDA toolchain
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Tiny Tapeout
Improving education and expertise in EE by making chip design accessible
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Silicon Compiler
Creating new SW products specifically designed for HW development workflows
However, there is still a significant gap between the large ecosystem of advanced tools and processes required to produce chips at scale and what is achievable today with purely OSS tools.
While a SW engineer may have some concept of using familiar tools that they can easily look up online or contribute to (e.g. a web framework such as React or Angular), HW engineers are often using in-house or third-party proprietary tools which are specifically designed to push Moore's Law to its limits. An exaggerated version of this would be to imagine if Meta and Google never open-sourced React or Angular, choosing instead to double-down on the view that their frontend frameworks captured trade secrets which gave them an edge over the competition.
Obviously, this is not a fair comparison — there are very fundamental differences between HW and SW development. HW development has significant upfront costs, export control restrictions (on designs and EDA tools), and a fine line between common methodologies and trade secrets. Additionally, the complex supply chain of semiconductors has given a significant concentration of control over advanced EDA tools to a few companies (Cadence, Synopsys, and Siemens). As a result, the daily tools that HW engineers use are conformed to fit the mold of the industry: hyper-specialized and proprietary. A lot of this is reflected throughout Chip War: The Fight for the World's Most Critical Technology by Chris Miller, which goes further into the deep history of semiconductor manufacturing as well as its relationship with geopolitics.
For many, this might seem like an obvious fact of life for a high-scale advanced manufacturing industry. (And conversely, for my OSS HW colleagues, this reality may seem more of a myth — many pieces of new HW do not rely on it at all.) I would generally agree, but with two nuanced claims:
Two Claims About the Future
Proprietary solutions may continue to persist at the bleeding edge, but AI complicates this picture
Regardless of the proliferation of OSS HW tools, the supply chain of the semiconductor industry may still trend towards favoring proprietary solutions for the most advanced nodes. Given the extraordinary difficulty of increasing transistor density while minimizing power consumption today, it makes sense that EDA vendors and chip designers are investing herculean efforts towards advancing their tools. Because of the cost of these efforts, it will be hard for OSS equivalents to keep pace at the frontier.
That being said, AI is actively reshaping this process. We are already seeing it applied to some of the hardest problems in chip design. Notably, the major EDA vendors themselves are racing to integrate AI into their own toolchains, which cuts both ways: it accelerates proprietary capabilities, but also signals that the underlying design intelligence may become more democratizable over time, potentially eroding the moat that proprietary tools have historically enjoyed.
HW companies will increasingly map their methodologies to OSS flows as they scale
Many methodology and workload scalability challenges faced by HW companies map to some version of a common SW problem. With enough creativity, it is possible to map OSS SW tools to these flows, meaning that we can solve the problem while improving the longevity of those flows by keeping them in line with SW industry trends and practices. This is one of my favorite parts of my role in architecting and implementing such systems, since they balance the boundary of solving real-world business issues and staying connected to the OSS community. I hope to publish more on my work in these areas soon w.r.t. build systems, CI/CD, and version control.
A Golden Age of Innovation
With both of these claims in mind, I think this is a golden age of innovation for HW companies. AI is making it significantly easier to advance HW design flows and mitigate the moats created by third-party software. I highly recommend a related post by Chris Lattner on this subject: The Claude C Compiler: What it Reveals About the Future of Software. AI may not be capable of writing a production-worthy C compiler today, but we can see the groundwork being laid for rapid changes in large-systems engineering. Additionally, AI significantly reduces the cost of migrating flows to new methodologies and integrating OSS tools with specific business needs. If a company needs to create a piece of HW infrastructure, why not figure out how to map that onto a large OSS project that our models can understand deeply?
So then, while there are many hurdles and challenges we will encounter in pushing semiconductors to the bleeding edge, I hope to convey a feeling of being at an inflection point — the past of silicon development still lays its shadows, but we will press on in advancing to the future.
And who knows, maybe soon I will be able to get out of using Perforce ;).